Job Title: Sr. ASIC Design Engineering Manager - CPU
Job Location: San Jose, CA or Portland, OR - hybrid on-site 2-3 days/week
Compensation: $200K - $300K+ Depending on experience plus bonus!
Requirements: ASIC Design, CPU Architecture, Engineering Management, RISC-V, Microarchitecture
Our company is a Founding Premier member of RISC-V International and a leading embedded processor intellectual property supplier in the world. We devote ourselves to developing high-performance/low-power 32/64 bit processors and their associated SoC platforms to serve the rapidly growing embedded system applications worldwide.
We have more than tripled our revenue in the last 5 years and were ranked among the "100 Fastest-Growing Companies" in 2020 by CommonWealth Magazine.
We are now looking for someone to lead our a team of CPU designers and DV engineers. Candidate must work on-site 2-3 days/week in San Jose, CA or Portland, OR.
1) Competitive Compensation ($200K - $300K+ Depending on Experience)
2) Comprehensive Benefits package including bonus!
3) The chance to join a well-established supplier of embedded CPU cores!
We are looking for someone to lead a team of CPU designers and DV engineers to build the next-generation of RISC-V CPUs. As a leader of this team, you will help guide design methodologies, analyze problems and devise best QoR solutions. Your responsibilities will include management of schedules, resources, hiring and office-site administrative tasks. Ideal candidates will be dynamic and have a profound passion for technical advances, CPU architecture, and leadership, coupled with a strong commitment to fostering a nurturing and supportive work environment for a diverse team consisting of both seasoned veterans and fresh-faced junior new graduates. Responsibilities include:
- Monitor production schedules, resource allocation, and workflow to ensure timely delivery of CPU IP.
- Lead and motivate a team of engineers, technicians, and support staff, fostering a positive work environment.
- Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
- Technical Documentation
- Responsible for efficiently working with multiple time zones, demonstrating effective autonomous management skills, and willingness to engage in late evening calls as required.
Must have a Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with 10+ years of experience:
- CPU Design & Engineering
- Engineering Management or team-lead experience
- Operations management or site management experience
- Proven experience within the semiconductor or CPU IP industry (RISC-V or similar experience a plus)
- Strong knowledge of CPU IP development processes, including RTL design and synthesis
- Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
- Experience using Verilog, System Verilog
- Strong mastery using Unix and scripting languages such as make, shell, perl or python
- Strong communication skills
- Excellent leadership and team management skills, with the ability to inspire and motivate a diverse team.
- Proven track record of long-term commitments, and a strong desire to contribute to our company's growth and success over an extended period.
So, if you are a Sr. ASIC Design Engineering Manager with CPU experience, please apply today! or send an updated copy of your resume to Mike.Vandenbergh@CyberCoders.com for immediate consideration!
BenefitsColorado employees will receive paid sick leave. For additional information about available benefits, please contact Mike Vandenbergh
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa.
Mike Vandenbergh is recruiting for this position and the positions below.
Email me to apply for this position
